The background description provided here is for the purpose of generally presenting the context of the disclosure. Work of the presently named inventors, to the extent it is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted as prior art against the present disclosure.
A multi-gate field-effect transistor (FET) incorporates more than one gate into a single device. The multiple gates may be controlled by a single gate electrode or by independent gate electrodes. Multi-gate FETs are one of the several strategies being developed by manufacturers to create smaller microprocessors and memory cells.
Initially, the term FinFET was used to describe a field effect transistor (FET) including a conducting channel that is wrapped by a thin silicon “fin”, which forms a body of the FinFET. A thickness of the fin (measured in the direction from source to drain) determines an effective channel length of the FinFET. A wrap-around gate structure improves electrical control over the conducting channel to reduce leakage current and overcome other short-channel effects. More recently, the term FinFET is used to generically describe any fin-based, multi-gate transistor architecture regardless of number of gates. Vertical gate all around (VGAA) FETs are similar in concept to FinFETs except that a gate material surrounds a channel region on all sides.
Formation of FinFET, VGAA and other structures such as buried bit lines (BBLs) are difficult due to the complexity and controllability encountered when forming a 3-D structure. Current methods limit the patterning size due to the method of doping that is used to produce conformal doping.